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r B. D. BEDFORD POWER CIRCUITS WHICH ARE INHERENTLY CAPABLE OF INVERTER OPERATION Qrignal Filed Nov. 13, 1962 6 Sheets-Sheet 1 fige.

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.Earn/'ce .Bea/fori Feb. 13, 1968 a. D. BEDFORD Re- 26,342

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POWER CICUITS WHICH ARE INHERENTLY Feb. 13, 1968 B, D, BEDFORD .Re. 26,342

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United States Patent O ABSTRACT 0F THE DISCLOSURE A family o] power circuits using a pair of conductivity controlled current switching devices interconnected inV series circuit relationship with a tapped first linear inductor across a pair ol power supply terminals that are adapted to be connected across-a source of electric potential. A load circuit is operatively coupled across the power supply terminals in series circuit relationship with at least one of the pair o] devices through a part of the tapped inductor. The circuits also include commutaziorr circuit means formed by at least orre commutating capacir'or and series connected second linear inductor operatively connected between the tap point o] the first inductor and at least one o] the power supply terminals. The series circuit comprised by the commutating capacitor and second inductor ls tuned to series resonance at a commutating Irequency having a period which is substantially shorter than the load current conducting periods of the power circuit. With this arrangement, one of the palr of current switching devices is adapted to be intermittently conductive for discharging the commutating capacitor through the topped first inductor and thereby terminating the conduction of the other of the pair of current switching devices. Bridge type power circuits comprising the same basic circuit configurations are also provided.

This invention relates to new and improved inverter circuits. V More particularly, the invention relates to a new and improved family of relatively inexpensive, elcent inverter circuits using silicon controlled [reflectors] rectifiers to convert direct current electric energy ino alternating current electric energy having a desired waveform.

With the introduction of the silicon controlled rectier into lndustry as a readily available and reliable electric current controlling component, considerable etort has been expanded in devising inverter circuit congurations fol converting direct current electric energy to alternating current having a desired waveform. While there are a number of inverter circuits available to the industry, many of these available circuits have operating characteristics which make them suitable for use only in certain situations. For other applications, these known inverter crcuts are not too satisfactory because their higher cost cannot be justified, relative ioemciency, lack ot flexibility, or adaptability to particular operating conditions, and other similar objections.

lt is, therefore, a primary object of the present invention to provide a new and improved family of general purpose inverter circuits which are relatively inexpensive to manufacture and etcient in operation.

ln practicing the invention, a new and improved inverter circuit is provided which includes a pair of gate controlled unidirectional conducting devices, which are preferably silicon controlled rectitlcra, and which are interconnected with a commutating interval current limiting reactor in circuit relationship. The circuit thus formed is adapted to be connected across a source of direct* current electric potential. A series circuit comprised byf at least one commutating capacitor and series connected second inductor is operatively connected through alten'- nate ones of the. unidirectional conducting devices to the source of direct current electric energy in a manner auch' that the capacitor' is charged to a predetermined energy level during the periods of conduction ot at least one of the gate controlled unidirectional conducting devices, and discharge of the commutating capacitor during cornmutatng periods will reverse bias the gate controlled-- unidirectional conducting device to cause it to turn olf. The series circuit comprised by the commutating capacltor and the second inductance is tuned to series resonance at a commutating frequency substantially higher than the operating frequency of the inverter. An additional unidirectional ooniuctng device, such as a diodels connected in parallel circuit relationship with each ot` th: gate controlled unidirectional conducting devices for" circulating the excess reactive energy stored in the commutating capacitor during the oommutating periods of the gate controlled unidirectional conducting devices. Additionally, auxiliary circuit means may be coupled to l the commutating interval current limiting reactor for circulating the energy stored therein during the oommutating periods of the gate controlled unidirectional conducting devices. ln a preferred embodiment of the invention, the commutating interval current limiting reactor comprises a center tapped winding wherein the two winding halves are tightly coupled so that equal currents owing in opposite directions in the winding halves produce arnpere turn elects which cancel each other out. To complete the circuit, a load is coupled to the unidirectionalconducting devices through the commutating interval current limiting reactor, and a gating signal source is operatively coupled to the gating electrodes of the gate controlled unidirectional conducting devices for gating on these devices in a manner to produce a desired output waveform.

Other objects, features. and many of the attendant advantages of this invention will be appreciated more readily as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein like parts in each of the several figures are identified by the same reference character, and wherein:

FIGURE l is a detailed circuit diagram of a new and improved, single phase inverter circuit constructed in accordance with the invention:

FIGURE 2 is a detailed circuit diagram of a second torm ot the new and improved single phase inverter circuit constructed in accordance with the invention and vhlr is preferred for use in connecjon with inductive FIGURE 3 is a detailed circuit diagram o! still a third form of the new and improved, single phase, half wave inverter circuit nstructed in accordance with the invention, and which is preferred for use with low voltage direct current power supply.

FIGURE 4 is a detailed circuit diagram of sill a fourth version ol the new and improved single phase inverter circuit constructed in accordance with the invention FIGURE S is a detailed circuit diagram of a threephase inverter employing a commutating circuit similar to that of the single-phase inverter of FIGURE l; and the nductively coupled feedback circuit of FIGURE 2;

FIGURE 6 is a detailed circuit diagram of a full wave inverter constructed in accordance with the present invention, and which employs as a part thereof the single phase inverter of FIGURE 2;

e l a FIGURE 7 is n detailed circuit diagram of a modified .version ot the full wave inverter circuit of FIGURE 6;

FIGURE 8 is n detailed circuitdiagram of still a third form of full wave inverter circuit constructed in accord- .ance with the present invention, but which does not relnuire a center tapped direct current power supply, and which employs as its basic building block the single phase inverter shown in FIGURE 4 of the drawings;

FIGURE 9a is a characteristic curve illustrating the voltage-time operating characteristics of the new and improved inverter circuits during commutation periods tor a' resistive load;

FIGURE 9b ia a current v. time characteristic curve of the new and improved inverter circuits during the communicating period for resistive load conditions;

FIGURE 10a is a characteristic curve illustrating the voltagetime operating characteristics of the new and improved inverter circuit for inductive load conditions;

FIGURE 10b illustrates the current v. time characteristics of the new and improved inverter circuits with inductive loads:

FIGURE lla is a voltage v. time characteristic curve for the new and improved inverter circuits operating with capacitive loads; and

. FIGURE lib ia a current v. time characteristic curve for the new and improved inverter circuits operating with capacitive loads.

The new and improved inverter circuit illustrated in FIGURE l of the drawing includes a commutating interval current limiting reactor comprised by a center tapped winding 1l formed of two winding halves 11a and 11h, with the two winding halves 11a and 1lb .being tightly coupled, and precisely matched for n reason which will be better appreciated hereinafter. The center tapped winding 11 is connected in series circuit relationship with a pair of gate controlled unidirectional conducting devices 12 and 13 which actually comprise silicon controlled recti- Sars. Silicon eoatroed rectiera are now well known in the industry. and have been adequately described in the liserature. Hence, no further identification of their chartctcristica is' believed required other than to state that they comprise essentially a solid ster.: version of a grid controlled gas discharge device wherein conduction through the device can he initiated by the application of a gating signal to the gating control electrode of the de vice, but thereafter the gating electrode loses control over conduction through the device and its anode or colleeter potential moet be reduced relative :o the cathode or emitter potential in order to tum the device od. For n f'rther description of the construction and operation of silicon controlled rectiflers, reference is made to the Sili- Controlled Rectifier Manual, Second Edition, publ by the Rectifier Components Department of the General Electric Company. West Genesee Street, Auburn, New York, copyright 196|. a copy of which can be obtained from the above identified Department of the General Electric Company.

In the inverter circuit of FIGURE l. the silicon controlled rectiiiera l2 and 13 atc connected in front to back series circuit relationship through the center tapped winding ll, with the series circuit thus comprised being connectedacrosstheterminalsldsndofadirectcurr'eitt power supply, not illustrated. Connected in parallel circuit relationship across the direct current power supply' with the series circuit comprised by the center tapped winding ll and the silicon controlled rectifiers l2 and l?, are a pair of series connected voltage dividing capacitors 16 and 11 whose center tap point is connected through a anitable load 18 to the center tap point of the center tapped winding ll. Also connected in parallel circuit relationship with the series circuit comprised by center tapped winding l1 and two silicon controlled rectilicra 12 and 13 are n pair of series connected commutating capacitors l! and 21 whose center tap point is connected through a second inductance 21 to the center tap point of the center tapped inductancc l1. To complete the circuit, additional unidirectional conducting devices comprised by diodes 23 and 24 are directly connected across each or' the silicon controlled rectiiicrs in parallel circuit relationship with respective ones of the silicon controlled rectiers. Further it is anticipated that a suitable gating signal source (not shown) will be coupled to the control gates 12g and 13g of the SCRs 12 and 13, respectively for turning the SCR's on and off in a manner to provide a desired output waveform. For a description of suitable gating circuits for this purpose, reference is made to chap.er 4 of the above identified SCR Manual.

In operation, at frequencies which are low with respect to the commutating frequency, the new and improved inverter circuit functions in the following manner: It is assumed that the silicon controlled rectifier 12 is conducting and that the silicon controlled rectifier 13 is in a turned off state. Under these eondit ons, load current will be supplied through the silicon controlled rectifier l2. to the load 18, and the commutating capacitor 2l will be charged to the full value of the direct current supply potential Enc. lf under these conditions, a gating on signal is supplied to the gating electrode 13g of the ailicon controlled rectier 13, and concurrently a turn o6 signal is applied to the gating electrode 12g of the silicon controlled rectifier 12, the SCR 13 will be rendered conductive, and at the same instant the SCR 11 will continue to conduct since the tum-off signal applied to the gating electrode 12g will have no etect on conduction through the SCR 12 but is applied merely for insurance purposes to assure that upon the SCR l2 being turned off, it will remain off. At this instant of time, both SCRs l2 and 13 will be conducting so that the full line potential Em is applied across both winding halves of the center tapped winding 11. As stated previously, the two winding halves 11a and 1lb of the center tapped winding 1l are exactly matched so that in effect at their center tap point the potential will be one half EDC. In other words, the potential applied to the terminal Z of load 1l is equal exactly to the potential Enc/2 applied to the remaining terminal X of the load 18 thereby assuring that no further load current is supplied to the load 18 and its value drops to zero. Since the commutating capacitor 2l was charged to the full value EN of the direct current power supply, it now discharges through the inductor 21 into the center tap of the center tapped winding 11 where it splits. half the commutat ng eu: rent i/2 going through the winding half lla and SCR l2, and the remaining half of the commutating current i/2 going through the winding half 11b and SCR 13. As previously stated, the center tapped inductance 11 is exactly matched and closely coupled so that the ampere turns flowing in the winding half lle due to the commutating current i/2 canoes out the ampere turns tlowing in the winding half 11h due to the commutating current i/2. and as n consequence the center tapped winding 11 does not look like an inductance to the commutating current. The commutating current ilowing in the upper winding half 11a opposes the load current liowing through the silicon controlled rectifier l1 so that the net current through the rectifier drops to zero, and the excess commutating current will flow through the diode 23 back into the commutating capacitor 19 to initiate charging of the commutating capacitor I9 to condition it for the next commutating cycle when it is required for the SCR 13 to be turned olf. The commutating current llowing in the lower half winding 11b is supplied through the SCR 13 and back into capacitor 2l. This current is in a direction to charge the capacitor 21 with a reverse polarity potential which conditions it for the next commutation cycle thereby greatly improving the efficiency of the circuit. concurrently, with this action, the excess commutating current flowing through the diode 23 produces a reverse bias across the silicon controlled rectifier 12 which assures it being turned olf. To facilitate this action, the second inductanoe 22, which together with the commutating capacitor 21 is series tuned to resonate at a commutating irequency which is substantially higher than the operating frequency of the inverter, but which allows the commutating current to build up sinusoidally for a period such that the initial sine wave pulse of commutating current exceeds the load current flowing through the SCR 12 for a period of time at least equal to the turn olf time of the SCR 12, thereby causing the above mentioned tum-oli' action to occur. This commutating frequency may be in the neighborhood of from two to one (2:1) to anywhere as high as 50,000 or 100,000 to one (50,000:1; l00,000:l) depending of course on the operating frequency of the inverte: and the turn oli time of the SCR. It is to be understood that the ratios cited above are not limiting but are merely cited as exemplary.

During the commutation interval (the period AT shown in FlGURE 9b), an additional current .al will begin to build up at a constant rate due to tue impressed direct current voltage EDC applied across the center tapped winding 11 which serves to limit the rate of increase of the direct current ilowing through the circuit during this interval. For this reason, the winding 11 is referred to as a commutation interval current limiting reactor and is designed so that it exhibits a minimum practical irnpedance to the load current, while exhibiting a maximum practical impedance to the build up of the additional current Al during the commutating interval. The rate of build up of the commutation interval current AI is dependent upon the inductance of the center tapped winding 1l, and upon the value of the voltage EDC as set forth by the expression di Ew tif- LI At the end of the commutation interval AT, this addi tional current will have the value Enc Al L" XAT While the current and voltage wave shapes shown in FIGURES 9a and 9b are for those assuming a resistive load 18, it is to be understood that this additional cornmutation interval current A1 will build up irrespective of the nature of the load.

Referring again to FIGURES 9a and 9b and assuming a resistive load 18, upon the commutating current i, shown in FIGURE 9b reaching a value equal to the load current iL plus twice the build up in commutating interval current (zal), current through the SCR 12 is reversed and cut-o commences. The commuating current ic continues to build up and maintains the reverse current through the SCR for a period equal to the cut oil time of SCR 12. During this period, diode 23 is rendered conductive, and maintains the commutating current i, while SCR 12 is cut off and returned to its blocking condition. Also during this period the commutating current i., reaches a peak, and begins to decay snusoidally toward zero until time t; wherc the nel current in the upper winding is zero, and the diode 23 begins to block. A linite clean out time is required for the diode 23 to block completey, however, so the commutation operation will continue until such time t, that diode 23 blocks. It is as;umed that the center tapped winding 11 has no leakage reactanoe for the purpose of this discussion, and that the cun'ent in the upper winding half 11a can be cut olf instantaneously. Aocordinglyf at the instant that the diode 23 blocks, the ilux level in the core of the center tapped winding 11 has built up from its precommutation level of Nml to a level of NAl+NmlL, and upon the diode 23 blocking, the current that had been owing in the upper winding half 11a has to be transferred to the lower winding 1lb (or to a secondary winding as will be discussed later). At the instant that the diode 23 blocks, two maior conditions must be satisfied upon the current being transferred to the lower winding half 1lb.

The lirst of these conditions is due to Lenzs law which requires that the flux level in the inductance 1l must be maintained at the value NUAI+NmIh and the second condition requires that the commutating current i., flowing in the inductance 22 be maintained to complete the commutation interval. This latter current also serves to precharge the capacitor 2l to a level EDC to condition it for the next commutating interval. Accordingly, upon diode 23 blocking, the point Z dnops from its mid-tap potential EDC/2 to a potential that is determined by the requirements of Lenz's law as set forth above. For example, it the commutating interval current AI is very small, the voltage of point Z in ell'ect will go to the negative D.C. potential; thereby assuming a condition where most of the effects of commutation are largely completed, and initiating a new half cycle of operation of the inverter. The stored energy in the inductance 22 and in the center tapped reactor 11 may cause a slight amount of oscillation oi the voltage of point Z, but such oscillation will die out due to the damping etect of the resistive load 18.

lf in contrast to the above defined condition, the ccmmutating interval current Al is sizeable compared to load current, the load current il, will assume a value which will satisfy the condition required by Lenz's law cited above. Under these circumstances, the voltage of point Z at time ta-lwill fall to a potential more negative than the value of the negative tenninal of the direct current power supply EDC. Subsequently, as the commutating interval current Al decre:ses to zero, the potential of the point Z will fall toward the value of the negative terminal of the direct cunent power supply -Egc allowing the load cunent iL to build back up to satisfy the requirements of I enzs law. Upon reaching this condition, the voltage o! point Z goes to the potential of the negative D.C. supply, and assumes a condition where the elects of commutation are largely completed, and initiates a new half cycle of operation. Again, if the commutating interval cunent AI is not too great with respect to load current, the voltage of point Z may oscillare due to the energy stored in the inductance 22 and reactor l1, but will be damped out by the effects of the resistive load.

In the event that commutating interval current AI is even larger compared to the load current, the potential at the point Z will tend to fall to a value considerably below the negative terminal of the direct current power supply EDC. To prevent this condition, a resistor shown in dotted lines at 25 can be coupled across the center tapped inductance l1 in the manner shown for circulating the energy trapped in the inductance ll so as to decrease the llux level in the reactance to the point such that the llux level in the core ot inductance l1 drops to a value equal to that iust prior to commutation (that is, equal to NugXIL). Upon this occasion, the core will be re:et by the net ampere turns being reduced to a value such that the llux level in the core is determined primarily by the load current, and the voltage of the point Z gocl to the potential of the negative terminal of the direct current power supply -E thereby assuming a condition where the major etlects of the commutation are completed, and initiating a new half cycle of operation. There is another technique (or meeting this problem which will be described with relation with the circuit shown in FIGURE 2 of the drawings, and which is probably a more satisfactory solution to the problem since dissipation of the energy stored in the center tapped winding 1l is not required, thereby improving the effi ciency of the inverter.

Another circuit modification which may beemployed with the basic inverter circuit of FIGURE l for protec tive purposes to limit the rate of rise of reapplied voltagi across the silcon controlled rectiflers l2 and 13 is th inclusion of a series connected resistor 26 and capacito 27 shown in dotted lines as being connected in paralle with the silicon controlled rectiers 12 and 13. Thi

7 resistance-capacitance network provides a path for the currentatthe instant thatthediodesandublock so as to reduce the induced voltage due to leakage inductance. Other schemes are available for this purpose, but will not be described since such techniques are well known in the art. The price paid for ths protective feature, in addition ,to the added components, is the loss of energy in the resistor 26. This loss may not be serious at low frequencies, but as the inverter frequency is increased, the losses may become signiiicant and may present heating problems in addition.

A second embodiment of the invention suitable for use as a single-phase inverter is shown in FIGURE 2 of the drawings. The embodiment of the invention shown in FIGURE 2 is similar in almost all respects to the circuit shown in FIGURE l. One maior diterence is that a common commutating capacitor 31 i3 used in place of the two commutating capactors l! and 21 of the circuit shown in FIGURE l. For this reason like parts in each of the two circuits have been given the same reference character. ln the circuit shown in FIGURE. 2 the cornmon commutating capacitor 3l is connected in series circuit relationship with the second inductnce 21, with the series circuit thus formed being series tuned to resonate at a commutating frequency which is substantially higher than the operating frequency of the inverter as was explained in connection with the circuit shown in' FIGURE l. The load 18 is connecled in parallel circuit relationship with the series circuit comprised by the commutating capacitor 31, and second inductnnce 22 be.ween the midtap points of the center tapped winding Il and the two voltage dividing capacitors 16 and l1. The second maior difference is the inclusion of a secondary winding 32 inductively coupled to the center tapped winding Il. The secondary winding 32 is connected in series circuit relationship with a blocking diode 33. The series circuit formed by secondary winding 32 and diode 33 is connected in parallel with the series circuits comprised by the center tapped winding 1I and the two series connected silicon controlled rectiliers l2 and I3.

The embodiment of the invention shown in FIGURE 2 is preferred for use in conjunction with inductive loads since it is better able to cope with the reactive component of the load cunen: stored in the load 20, as well as the excess energy built up during the commutating interval. This feature is obtained by the inclusion of the secondary winding 31 and blocking diode 33 which, of course, could be incorporated into the embodiment of the circuit shown in FIGURE l in place of the resistor 25. Fabrication of the circuit to include this feature allows excess energy drawn from the oower supply during commutation, to be recirculated back into the power supply, thereby conserving the energy, and greatly improving the efficiency of the inverter. ln operation at frequencies which are low, with respect to the commutatlng frequency, the commutating capacitor 3l will be charged to substantially half the value of the direct current power supply Em during each cycle of operation of the controlled rectifier l2 or 13. For example, if the SCR 12 is conducting, commutating capacitor .3l will be charged so that the pcint Y is positive with respect to the point X to half the value of the direct current power supply Enc. If at this point the SCR 13 is gated on by the gating signal source while a turn off signal is applied to the gating electrode of the SCR l1, the colnmuiating current i, will flow out of the commutating capacitor 3l and through both winding halves lla and lib of the center tapped inductance 1I in opposile directions to turn oh the SCR l2 in the manner described with relation to the circuit shown in FIGURE l. Similarly, because the full value of the direct current power supply Enc is supplied across the winding 1I, an additional curlent will be built up during the commutating interval in the manner described with relation to the circuit shown in FIGURE 1. Here again, this additional current AI ls minimized because the reactor 1l is designed to exhibit a minimum practical impedance to the load current while exhibiing a maximum practical impedance to the build up of the additional current AI during the commutating interval.

The operation of the inverter circuit with an inductive load represents the most severe condition presented for commutation since wiih an inductive load it is necessary that the commutation current not only perform the operation of turning ci the SCR (as in the resistive and noload sftuations), but in addition it mus: supply current to the load during a portion of the commutation interval. This is caused by the nature of the inductive load. FIG- URE 10a and FIGURE 10b illustrate the pertinent voltage and current wave forms obtained during the commutation interval with the circuit shown in FIGURE 2 of the drawings. In FIGURE IIJ'J it can be seen that at the sart of the commutation interval, the load current I., is supplied to the load. As the commutation current ic begins to build up from zero, ie flows into the load decrezsng the amount of the current required from the SCR l2. At one point, the current le is just equal to the load current iso that the load requires no current from the SCR l2, and the current through SCR 11 is reduced to one half the load current (neglecting Ai) and the current in .he SCR 13 has built up to one haif the load current so as to maintain the flux level in the center tapped winding ll in accordance with the requirements of Lenzs law. As the commutation interval continues, the commutating current i., builds up unil i,I equals twice the load current iL, plus the build up in commutating interval current Ai, at which pcint current in SCR I3 is reversed, and cut-oli commences. The commutating current i, continues to build up and maintains the reverse current through the SCR for a pericd equal to the cut'o time of SCR l2. During this pericd, diode 23 is rendered conductive and maintains the commutation current whie the SCR I2 is turned off, and returned to ils blocking condition. Also during this period, the commutating current i, reaches a peak and starts to decay sinusoidally toward zero. At time t1, the commutation current i,a and the load current if, through the upper winding half Ila is equal to twice the build up current Ai (i.e., Zai) so that the diode 23 begins to block. At time t, the diode Z3 has completely blocked so that the load current il, is now flowing entirely through the lower branch 1lb. At time t, the current which flows through the lower winding half 1lb is determined by the difference between the comrnuating current i, and the load current il, that has built up, since both of these currents must be maintained when the diode 23 blocks due to the inductances in each path in accordance with the requirements of Lenz's law. It may be seen in FIGURE 10b that the current through the lower winding 1lb at time t, is less than I At the point of time just prior to commutation, the ux lev`el built up in the center tapped winding ll was equal to NmXIL, and since there has been a net increase of ilux due to the build up of the commutating interval current AI during the period AT, it is necessary that the secondary winding 32 conduct in order to maintain the flux level of the center tapped winding ll. For this to happen, the potential of the point Z must drop below the value of the negative terminal of the direct current power supply in order tn render diode 33 conductive. With the potential of pcint Z below the negative terminal of the direct current power supply, the voltage between the points X and Z is increased, thereby allowing more commutating current i., to be drawn frcm the commutating capacitor 3l. This occurs between the intervals t, and tl. This additional current also tlows in the lower winding half 1lb and builds up to a maximum before it tegir-.s to sinusoidally decay back towards zero at a frequency which is approximately the same as the frequency of commutation since only the leakage inductance of the lower winding is seen when the secondary winding 32 is conducting. At thc instant the commutating current i, reaches the value ig, and begins to decrease below that value, the energy stored in the load inductance 13 begins to supply current through the return diode 34 back through the lowur winding half 1lb into the load. This how of current in the reverse direction through the lower winding half 11u requires that the secondary winding 33 conduct even more current than before in order to maintain the llux level of the center tapped winding l1. For this reason, the iode 33 will remain conducting until the core of the center tapped induciance l1 has been reset by the net anzpere turns being reduced so that the flux level in the crte is determined primarily by load current. Goce the ture has been reset, the maior effects of commutation are completed and the load current flows to the load through the return diode 14. This current de creases linearly with time as shown in FIGURE l0b until the energy in the load inductance is exhausted, at which point the current then reverses and begins to liow through the silicon controlled recilier 13 building up during the next half cycle of operation of the inverter until the next commutating period. Prom the above discussion it can bs appreciated that the after elects of `commutation mentioned briefly in connection with the resistive load case are quite pronounced in the case of an inductive lor d. As discussed previously, a resistive load tends lo dampen the oscillatory current which results when the diode 33 or 24 blocks, and the additional stored capacitor energy in the commutating capacitor is being discharged. In the inductive load case. this oscillation becomes more severe than for the resistive load case due to the additional trapped energy in the circuit components resulting from the inductive load current.

As shown in FIGURES lla and 1lb of the drawing. operation of the new and improved inverter circuit with a capacitive load is somewhat similar to no-load operation of the inverter. Because of the leading load factor caused by the capacitive load, the load current will be dowing through the return diode 2.3 ust prior to commutation, assuming that the circuit is in the condition where the SCR 12 is in a condition such that if the polarity of the potentials across it were correct, it would conduct, and SCR's are turned oli'. Upon initiating the commutation cycle by turning on SCR 13. the commutation current i.1 will llow up through the return diode in winding half 11a adding to the load current, and the other half of the commutation current i, llows through the lower winding half 11b and SCR 13 in the usual manner. In this case the commutation current i, llowing in the upper winding half 11a and return diode 23 is re dundant since the silicon controlled rectifier 12 was already baebbiased due to the leading load current through the return diode 23 lust prior to commutation. As shown in FIGURE 11b, the net current in the upper winding half 11a is not reduced to zero until time tl when the current in the upper winding half 11a is iust equal to the build up current AI. At this point the return diode 23 will begin to block, thereby completing the commutation interval. Prior to this occasion, the SCR`11 has, of course. been turned oli' due to the back-biasing effect of the return diode 23 upon conduction through the SCR 13 having been initiated. It should he noted that the cornmutation interval AT in the case of the capacitive load is increased considerably over that observed with other load conditions.

The embodiment of the invention shown in FIGURE 3 of the drawings is somewhat dilierent from the single phase inverter circuits shown in FIGURES l and 2 in that the emitter electrodes of both silicon controlled rcotiliera 12 and 13 are coupled to the negative terminal of the direct current power supply EN in common, with the collector electrodes of the SCRs being connected to the ends of respective winding halves 37a and 37b of supply. To satisfy center tapped winding 37. The center tapped point of the center tapped winding 31 is connected through a commutating interval current limiting reactor comprised by a primary winding ll, to the positive terminal of the direct current power supply Enc. The commutating inten val current limiting `winding l1 is inductively coupled to a secondary winding 31 connected in series with a blocking diode 33 across the direct current power supply 4Ew. A commutating capacitor 35 is connected in series circuit relationship with a second inductance 36 between the collector electrodes of the silicon controlled rectitiers 13 'and 13 with the series circuit thus comprised being tuned to series resonance at a commutating frequency which is substantially higher than the operating frequency of the inverter. Load current is supplied from the inverter circuit of FIGURE 3 through a secondary winding 33 that is inductively coupled to the center tapped winding 37 and that has a load 39 connected across it.

1n operation, the circuit of FIGURE 3 functions in a manner similar to the circuits of FIGURES l and 2. Aasummg the silicon controlled rectifier 12 is to be conducting and SCR 13 to be turned off, the commutating capacitor 35 will be charged so that the point X is at the potential of the negative terminal of the D.C. power supply Ew and the point Y is charged to double the positive potential -l-Eo. Upon SCR 13 being turned on. the point Z will be connected to the same potential as the point X.and both points will in etfect be at the same potential as the negative terminal ot. the direct current power suppl y Ew The charges trapped in the commutating capacitor 35 upon this occurrence will llow through the SCR 13 and the SCR l2 reducing the load current through SCR l2 to zero, with the surplus commutating current flowing through the diode 23 to produce a reverse bias on SCR l1, and turn it off. 0n the alternate half cycles the reverse process takes place to commutate off the SCR 13. During the commutating interval the additional current AI built up during thecommutating interval will flow into the center [top] rap point on the winding 37, split, and supply equal currents in opposite directions through the winding halves 37a and 37b. As a consequence, the ampere turn effects of these currents will cancel each other out, and the winding 37 will not appear as an impedance to this additional current. In order to prevent this additional current Al from increasing at too great a rate, the commutating interval current limiting reactor winding 11 is included in the circuit. This winding 1l is designed to exhibit a minimum practical impedance to the load current while exhibiting a maximum practical impedance to the build-up of the additional current AI during the commutating interval. Because the winding 11 does exhibit some impedance to the load current Il, llux is built up in the core of the winding l1 during the load current carry interval as aet forth in the expression Nnlg. During the commutation interval, [Lenz] Lenzs law requires that this ux level be maintained until it is allowed to decay at a iinite rate limited by tbe tinite voltage of the direct current power this requirement the secondary winding 32 conducts. and recirculates the cunent induced therein by the dux change in winding 11, back into the D.C. power supply. ln this manner. the energy associated with the ux in winding 11 is not dissipated but is conserved thereby improving the efficiency of the circuit while allowing the energy stored in winding ll to decay at the above mentioned finite rate. Ooncurrently, the charge on the commutating capacitor 35 will oscillate around the series tuned circuit comprised by the commutating capacitor 35 and second inductance 36. recharging the capacitor 35 in a reverse polarity direction. and commutating of! the SCR 11. Upon this occurrence, the potential of the point Z will go to the potential of the negative terminal of the di. rect current power supply Em. thereby completing the commutation interval, and initiating a new half cycle of operation.

Still a fourth version of a single phase inverter circuit constructed in accordance with the invention is shown in FIGURE 4 of the drawings. The embodiment of the single phase inverter circuit shown in FIGURE 4 is similar in all respects to the inverter circuit illustrated in FIG- URE l with the exception that the single inductcr 22 of the FIGURE I circuit is replaced by two separate inductors 3 and 4l in the inverter of FIGURE 4. The inductor 39 and series connected capacitor 19 are tuned to series resonance at the commutating frequency of the inverter as also are the inductor 41 and the capacitor 2l. Additionally, a secondary winding 32 is inductively coupled to the commutating interval current limiting reactor comprised by the center tapped winding 11, and is connected in series circuit with a blocking diode 33 across the direct current power supply. By this arrangement, the auxiliary circuit means comprised by winding 32 and diode 33 serves to feed back the excess reactive energy in the winding 1l to the direct current power supply in the manner described wilh relation to FIGURE 3 of the drawings. In all other respects, the circuit oi FIGURE 4 operates in a fashion that is so similar to that described with relation to FIG- URE I of the drawings, that it is believed unnecessary to again describe it in detail.

A three-phase inverter circuit constructed in accordance wi.h the present invention is shown in FIGURE 5 of the drawings. The three-phase inverter of FIGURE S is actually constructed from three single-phase inverters of the type shown in FIGURE l of the drawings, and, hence, cach of the single-phase inverters has been identilied with the same reference character employed in connection with the description of FIGURE l of the drawings. Because each of the three single-phase inverters employed in the FIGURE 5 circuit are constructed and operate in an essentially identical manner of that described in relation to FIGURE l. they will not be again described in detail. The outputs of the three single-phase inverters are combined in a delta connected load circuit comprised by one load 42 being connected between the center tap points of the center tapped windings 1I and Il', a load 43 connected between the center tap points of the center tapped windings Il' and Il", and a load 44 connected between the center tap points of the center tapped windings Il and 1I". It would also be possible to combine the outputs in a Y connected load circuit with or without a neutral connected to ground. or with a neutral connection back to the neutral of the direct current power supply. By interconnecting the individual loads of the single phase inverters in any of the above manners, the outputs of the inverters can be combined to provide a three-phase optput. It is of course necessary that the timing of the gating-on and turn-olf signals applied to the gating electrodes of the several SCRs be properly synchronized by the gating signal sources. For this reason, the gating signal source must be specially tailored for three-phase operation, in the manner oi those illustrated, and described on pages 130 and 133 of the above described SCR manual.

A single-phase, full-wave bridge inverter constructed in accordance with the invention is shown in FIGURE 6 ot the drawings. The full wave bridge inverter of FIG- URE 6 employs two of the basic single-phase, full-wave inverter circuit arrangements of FIGURE 2 modified to provide full wave operation. To form the full-wave bridge inverter circuit of FIGURE 6, the voltage dividing capacitors 16 and I7 of the single-phase full-wave inverter of FIGURE 2 have been replaced with a second set of series connected silicon controlled rectiers I2' and I3' and center tapped winding Il' shown on the left hand portion of the circuit as viewed by the reader. In operation, the full-wave bridge inverter of FIGURE 6 functions in essentially the same manner as two single-wave inverters, but must employ an appropriate gating signal source for providing gating signals to the gating electrodes of the silicon controlled rectiliers to achieve full wave operation. Because of the tact that the inverter of FIG- URE 6 employs a common commutating capacitor 3l,

12 itisnecessarythattheSCRsbegatedon andotfina closely controlled manner to avoid complications in operation of the circuit.

In order to obviate the need for rigorous synchronization of the firing of the SCR's for the circuit shown in FIGURE 6 of the drawings, the full wave inverter of FIGURE 7 has been provided. The full wave inverter of FIGURE 7 is similar to the inverter of FIGUR-E 6 with the exception that two commutating circuits cornprised by tne commutating capacitor 31 and second inductance 21 and commutating capacitor 31' end serond inductance 12' have been provided, in place of the single commutating circuit used in the embodiment shown in FIGURE 6. In the full wave bridge inverter of FIGURE 7, a pair of series connected voltage dividing capacitors 16 lind 17 are connected across the direct current power supply Enc with the mid-point of the voltage dividing capacitors being connected through the series commutating circuit comprised by commutating capacitor 31 and second inductance 22 to the mid-tap point of the center tapped winding l1. Similarly, the center point of the voltage dividing capacitors 16 and 17 is connected through a second series commutating circuit comprised by the commutating capacitor 31 and series connected second inductance 22' to the center tapped point of the center tapped winding Il'. The load I8 to be supplied is connectcd between the center tap point of the two center tapped windings Il and l1'.

In operation, the full wave bridge inverter of FIGURE 7 functions in an essentially similar fashion to two singlephase inverters of the type shown in FIGURE 2 of the drawings operated in a bridge inverter manner to provide a full wave output signal. Because separate commutating circuits are provided for each of the center tapped windings 1I and Il', it is no longer essential to so closely synchronize the turning cn and turning oli of the various silicon controlled rectiers as was the case with the full wave inverter shown in FIGURE 6 of the drawings. It should be noted, however, that both the full wave inverters shown in FIGURE 6 and FIGURE 7 require a center tapped direct current power supply which increases the cost of the inverter somewhat. I'o obviate this need, a circuit such as that shown in FIGURE B of the drawings is provided.

The full wave bridge inverter shown in FIGURE 8 of the drawings is comprised by two single-phase inverters of the type shown in FIGURE 4 interconnected through a common load 18 to provide a full wave output. Because the full wave bridge inverter of FIGURE 8 is essentially no different in operation and construction from two single-phase inverters of the type illustrated and described with relation to FIGURE 4 of the drawings, the various parts of the circuit have been identified by the same reference numerals, and a further description of the construction and operation of the circuit is believed unnecessary. It should be noted, however, that the full wave bridge inverter ot' FIGURE 8 does not require a center tapped direct curent power supply even though it does require two additional inductances and two additional commutating capacitors.

It is believed obvious from an examination of FIG- URES 6-8 that the gating signal sources used to gate on the various silicon controlled rectilers will be somewhat more complex than those used with the single-phase inverters illustrated and described in connection with FIGURES 1 4. Suitable gating signal sources for use with full wave bridge inverters have been described heretofore in the literature (for example, see the above identified Silicon Controlled Rectifier Manual), and, hence, a detailed description of their constnrction and operation is believed unnecessary. Further with respect to circuits shown in FIGURES 7 and 8, because of the use of the individual conunutation circuit branches in these circuits, it is possible to use these circuits in conjunction with a phase controlled gating signal source 13 similar to those described in the above identitied SCR Manual, to deliberately alter the phase relation of the tiring of the SCR's in this circuit for voltage control purposes. Since such technique is well known in the control of bridge inverter circuits, a further description of the same is believed unnecessary.

lt should be noted that in the foregoing description, it was assumed that the commutating frequency was suhstantially higher than the operating frequency. For the purpose of this paragraph. this relationship shall be defined as constituting the portion of the spectrum where a half period of the commutating frequency is no more than one tenth (IAQ) a half perind of the operating frequency. In the event that the inverter is designed to operate in a region where the commutating frequency is lsuch that its half period extends from about one-half (l) to nine tenths (9&0) a half period of the operating frequency, the operation becomes more complex. In operating under these latter assumed conditions, the dissipation of the energy stored in the commutating interval eurent limiting reactor will extend over a substantial portion (i.e. A to 95) of the operating half period. Accordingly, since the transients associated with commutation extend over a substantial portion of the operating half cycle, it is anticipated that the wave-shape of the output signal will not be quite so good as that which could be maintained while opendag under other not so rigorous conditions.

From the foregoing description, it can be appreciated that the invention provides a new and improved family of general inverter circuits which are relatively inexpensive because of the fact that it does not require additional silicon controlled rectiliers to eommutate olf the load current carrying rectitiers. Additionally, because the commutating energy stored in the commutating circuits of the inverter is recirculated and used to charge the commutating circuit in a reverse direction following each half cycle of operation, the etliciency of the new and im proved inverter is comparatively high.

Having described several embodiments of the new and improved inverter circuits constructed in accordance with the invention, it is believed obvious that other modilications and variations of the invention are possible in light of the above teachings. It is, therefore, to be understood that changes may be made in the particular embodiments of the invention described which are within the full intended scope of the invention as defined by the appended What I claim as new and desire to secure by Letters Patent of the United States is:

l. A new and improved inverter including in combination a pair of gate controlled unidirectional conducting devices, a commutating interval current limiting reactor interconnected with the pair of gate controlled unidirectional eonducting devices with the circuit thus formed being designed for connection across a source of direct current electric potential, a commutating circuit comprised by at least one commutating capacitor and series connected second inductor operatively connected through at least a portion of the commutating interval current limiting reactor and through alternate ones of the unidirectional conducting devices during periods of conduction of the same across the source of direct current electric energy whereby the commutating capacitor is charged to a predetermined energy level during periods of conduction of respective ones of said gate controlled unidirectional conducting devices, and means for gating on the non-conducting one of the gate controlled unidirectional conducting devices to discharge [of] the commutating capacitor and reverse bias the initially conducting one of said gate controlled unidirectional conducting devices to turn it olf, the series circuit comprised by the commutating capacitor and second inductor being tuned to series resonance at a commutating frequency substantailly higher than the operasing frequency of the inverter.

2. The combination set forth in claim t further characterized by an additional unidirectional conducting device directly connected across each of the gate controlled unidirectional conducting devices in parallel circuit relation-` ship for circulating any excess reactive energy of the commutating capacitor during the commutating periods of the gate controlled unidirectional conducting devices.

3. The combination set forth in claim 1 further characterized by auxiliary circuit means operatively coupled to said commutating interval current limiting reactor for circulating the energy stored therein during the commutating period.

4. The combination set forth in claim 1 wherein the commutating interval current limiting reactor is a winding which is tapped at its midpoint with the two winding halves being tightly coupled so that equal currents flowing in opposite directions in the winding halves produce ampereturn effects which cancel each other out.

5. The combination set forth in claim l further characterized by a load operatively coupled to the source of electric potential through said unidirectional conducting devices.

6. The combination set forth in claim l wherein said gate controlled unidirectional conducting devices comprise silicon controlled rectitiers.

7. The combination set forth in claim 1 wherein the gate controlled unidirectional conducting devices comprise silicon controlled rectiers and wherein the commutating interval current limiting reactor is a winding which is tapped at its center point with the two winding halves being tightly coupled so that equal currents flowing in opposite directions in the winding halves produce ampereturn effects which cancel each other out. and further characterized by auxiliary circuit means operatively coupled to said commutating interval current limiting reactor for circulating any excess ing the commutating period, a load operatively coupled to the source of electric potential through said silicon controlled rectiliers, and an additional unidirectional conducting deviee directly connected across each of the gato controlled unidirectional conducting devices in parallel circuit relationship for circulating any excess reactive energy of the commutating capacitor during the commutating periods of the gate controlled unidirectional conducting devices.

8. The combination set forth in claim 2 wherein said gate controlled unidirectional conducting devices comprise silicon controlled rectifiers, and said additional unidirectional conducting devices comprise diodes.

9. A new and improved inverter including in combination a pair of silicon controlled rectifiers, a commutating interval current limiting reactor comprised by a center tapped winding interconnecting the pair of silicon com trolled rectitiers in series circuit relationship, a pair of voltage dividing capacitors connected in series circuit relationship and adapted to be connected across a direct current source of electric energy in parallel circuit relationship with the series circuit comprised by the center tapped winding and silicon controlled rectifiers, a commutating capacitor and second inductance interconnected in series circuit relationship between the iuncture of the voltage dividing capacitors and the center tap point on the center tapped winding, the commutating capacitor and second inductance being tuned to series resonance at a commutating frequency that is substantially higher than the operating frequency of the inverter, and a respective by-pass diode directly connected across each one of said silicon controlled rectiers in parallel circuit relationship.

10. The combination set forth in claim 9 further characterised by auxiliary circuit means operatively coupled to said center tapped winding for circulating the energy stored in said tapped inductance during the commutating periods.

ll. A new and improved inverter including in combination a pair of silicon controlled rectrti ers, a comenergy stored therein durl mutsting interval current limiting reactor comprised by a center tapped winding interconnecting the pair of silicon controlled rectiers in series circuit relationship, a lirst pair of voltage dividing capacitors connected in series circuit relationship and adapted to be connected across e direct current source of electric potential in parallel circuit relationship with the series circuit comprised by the center tapped winding and silicon controlled recttliers, a pair of commutating capacitors connected in series circuit relationship in parallel with the series circuit compriced by said center tapped winding and silicon controlled rcctiliers, and with the voltage dividing capacitors. a second inductance interconnected between the juncture of the commutating capacitors and the center tap on the center tapped winding with s load being adapted to be connected between the center tap on the center tapped winding, and the juncture of the voltage dividing capacitors, said second inductance being of a value to tune the series circuit comprised by the second inductance and either of the commutating capacitors to series resonance et s commutating frequency that is substantially higher than the operating frequency of the inverter, and a respective diode directly connected across each one of said silicon controlled rectifiers in parallel circuit relationship.

12. The combination set forth in claim 11 further characterized by auxiliary circuit means operatively coupled to said center tapped winding for circulating the energy stored in said center tapped winding during the commutating interval.

13. A new and improved inverter including in combination a pair of silicon controlled rectiliers, a center tapped winding interconnecting one set of like electrodes o! the pair of silicon controlled rectiters, the remaining set of like electrodes of the pair of silicon controlled rectillers being adapted to be directly connected in common to one terminal of a direct current source of electric potential, s commutating interval current limiting reactor interconnected between the center tap ofthe center tapped winding and the remaining terminal of the source of direct current eledric potential, a commutating capacitor and inductance connected in series circuit relationship between the tirst mentioned set of like electrodes ot' the silicon controlled rectiters and in parallel with the center tapped winding, the commutating capacitor and inductsnce being tuned to series resonance at a commutating lrequency substantially higher than the operating frequency of the inverter, and a respective by-pass diode directly connected across each of said silicon controlled rectitiers in parallel circuit relationship.

14. The combination set forth in claim 13 wherein said commutating interval current limiting reactor comprises a third winding, and wherein said inverter circuit is further characterized by means for coupling s load to the center tapped winding, and auxiliary circuit means operatively coupled to said third winding for circulating the energy stored in said third winding during commutating periods.

1S. A new and improved inverter including in combination s pair of silicon controlled rectiliers, a commutating interval current limiting reactor comprised by a center-tapped winding interconnecting the pair of silicon controlled rectilers in series circuit relationship, a pair of voltage-dividing capacitors connected in series circuit relationship across s direct current source of electric potential in parallel circuit relationship with the series circuit comprised by the center-tapped winding and silicon controlled rectiers, two commutating series circuits with each series circuit being tuned to series resonance at a commutating frequency substantially higher than the operating frequency of the inverter and being formed by a comi mutating capacitor and s second inductance connected in series circuit relationship, the two series circuits thus formed are in turn connected in series circuit relationship scro the direct current source of electric potential inparallelwiththeseriescircuitcomprisedbytbeceoter tapped winding and silicon controlled rectiliers, means connecting the juncture of the two commutating series circuits to the center tap point on the center tapped winding with the inverter being adapted to have a load connected between the juncture of the voltage dividing capacitors and the juncture of the series commutating circuits, and s respective diode directly connected across each oi said silicon controlled rectifiers in parallel circuit relationship.

16. The combination set forth in claim l5 further characterized by auxiliary circuit means operatively coupled to said center tapped winding for circulating the energy stored in said tapped inductance during the commutating periods.

17. A new and improved multi-phase inverter employing the single-phase inverters of the type set forth in claim 1 wherein the loads of the individual inverters are interconnected to provide a multi- 18. A new and improved multi-phase inverter comprising three single phase inverters of the type set forth in claim 9 wherein the loads are effectively interconnected between the center taps of the center tapped windings in the first and second inverters, the second and third inverters, and the trst and third inverters.

19. A new and improved full wave bridge iggrter including in combination two series circuits a apted to be connected in parallel circuit relationship across a direct current source of electric potential, each of said series circuits being comprised by a pair of silicon controlled rectiers and a center tapped winding interconnecting the pair of silicon controlled rectitiers in series circuit relationship, a commutating capacitor and second inductance interconnected in series circuit relationship between the center taps of the center tapped windings of each of said first mentioned series circuits, the commutating capacitors and second inductance being tuned to series resonance at a commutating frequency substantially higher than the operating frequency of the inverter with the inverter being adapted to have a load connected in parallel with the commutating circuit between the center taps of the first mentioned center tapped winding, a respective diode directly connected across each of the silicon controlled rectiiiers in parallel circuit relationship, and auxiliary circuit means operatively coupled to each ot said center tapped inductances for circulating the energy stored in said center tapped inductances during the commutating periods.

20. A new and improved full wave bridge inverter including in combination two series circuits adapted to be connected in parallel circuit relationship across a direct current source of electric potential, each of said series circuits being comprised by a pair of silicon controlled rectiliera and a center tapped winding interconnecting the two silicon controlled rectiers in series circuit relationship, a pair of voltage dividing capacitors connected in series circuit relationship, with the series circuit thus formed being connected in parallel circuit relationship with both said tirst mentioned series circuits, rst and second commutating circuits each comprised by a series connected commutatng capacitor and second inductance tuned to series resonance at a commutating frequency substantially higher than the operating frequency of the inverter, one cad of said first and second commutating circuits being connected in common to the juncture of the voltage dividing capacitors with the remaining ends of each commutating circuit being connected to the center tap points of respective ones of said center tapped winding, a respective diode directly connected across each one of said silicon controlled reetiters in parallel circuit relation ship, and auxiliary circuit means operatively coupled to each of said center tapped windings for circulating the energy stored in said center tapped winding during the commutating interval.

2l. A new and improved full wave bridge inverter cir- W illluin itl combination two series circuits adapted 17 tobeconnectedinparsllelcircuitrelationship scrosss direct current source of electric potential, each ci said series circuits being comprised by a pair of silicon controlled rectiliers and s center tapped winding interconnecting the two silicon controlled rectiers in series circuit relationship, s set of two commutating circuits connected in parallel circuit relationship with said lirst mentioned two series circuits, each of said sets of commutating circuits comprising two series connected circuits, with each circuit being comprised by a capacitance and a series connected second inductance tuned to series resonance at s commutsting frequency that is substantially higher than the operating frequency of the inverter, the center tap of the center tapped winding in one of said lrst mentioned series circuits being connected to the iuncture of the two series connected circuits in one o! said sets of commutatlng circuits, and the center tap of the center tapped wind- ,ing in the remaining first mentioned series circuit being connected to the juncture of the two series connected circuits in the remaining one of said sets of commutating circuits with s load being adapted to be connected between the center tap points of the center tapped windings in said lirst vmentioned pair of series circuits, a respective diode directly connected across each one of the silicon controlled rectiliers, and auxiliary circuit means operatively coupled to each of said center tapped windings for circulating the energy stored in said center tapped windings during the commutating periods.

22. The combination set forth in claim 2Q further charscterizcd by s load interconnected between the center tap points o! the two center tapped windings, and gating signal means operatively coupled `to the gate electrodes of the silicon controlled rectifier: for phase controlling the gating-on of said silicon controlled rectiliers to thereby control the sagnitude of the bridge inverter output.

23. The combination set forth in claim 21 further charscterized by a load interconnected between the center tsp points of the twocenter tapped windings, and gating signal means operatively coupled to the gate electrodes of the silicon controlled rectiliers for phase controlling the gatingon of said silicon controlled rectiers to thereby control the magnitude of the bridge inverter output.

24. A new and improved power circuit including in combination a pair of gate controlled current switching devices, a commutatlng interval current limiting reactor interconnected with the pair of gate controlled current switching devices with the circuit thus formed being designed for connection across, a source of electric potential, a commutarlng circuit comprised by at least one commutating capacitor and series connected second inductor operatively connected through at least a portion of the commutatlng interval current limiting reactor and through alternate ones of the current switching devices during periods of conduction .of the same across the source of electric potential whereby the commuta:ing capacitor is charged to a predetermined energy level during periods of conduction of respective ones of said gate controlled current switching devices, and means for gating on the non-conducting one of the gate controlled current switching devices lo discharge the commutalng capacitor and reverse bias the initially conducting one of said gate conrrolled current switching devices to turn it o, the series circuit comprised by the commutating capacitor and second Inductor belng tuned to series resonance at a cornmutaring frequency having a period substantially shorter than the load current conducting periods of the power circuit.

25. The combination ser forth ln claim 24 further characterized by a unidirectional conducting device directly connected across each of the gate controlled current switching devices ln reverse polarity parallel circuit relationshlp for circulating any excess reactive energy of the commurating capacitor during the commutaring periods of the gale controlled current switching devices.

acterized by auxiliary circuit means operatively couplcab.

to said commutatirig inrerval current limi :ing reactor for circulating the energy stored therein during the commuraiing period.

27. The combination set forth in claim 24 wherein the commutatlng interval current limiing reactor is a winding. which is tapped at its midpoint with the two winding: halves bring tightly coupled so that equal currents flowtng in opposite directions in the winding halves produceampere-turn eects which cancel each other out.

28. Tire combination ser forth in claim 24 further characterized by a load operafrvely coupled across the source of electric potential through at least one of said gate controlled cftrrent switching devices.

29. The combination set forth in claim 24 wherein sold gate controlled current switching devices comprise silicon controlled rectlfiers.

30. The combinationset forth in claim 24 wherein the gate controlled, current switching devices comprise silicon t controlled recifiers and wherein the commut'aiing interval current limiting reactor is a winding which is topped ab its center point with the two winding halves being tightly coupled so that equal currents flowing in opposite directions ln the winding `halves produce ampere-turn eects which cancel each other out, and further characterized by auxilim'y circuit means'operatt'vely coupled to said com. maia ing interval current limiting reactor for circulatlng any excess energy stored therein during the commutatlng pcrlcd, a load operatively coupled across the source of electric potential through at least one of said silicon controllcd recrt'fiers, and a unidirectional conducting device directly connected across each of the silicon controlled rectifiers in reverse polarity, parallel circuit relationship for circulming any excess reactive energy of the commurating capacitor during the commutaring periods of the gate controlled devices.

3l. The combinados: set forth ln claim 24 wherein mld gate controlled current switching devices comprise silicon controlled rectlfiers, and said unidirectional conducting devices comprise semiconductor diodes.

32. An improved power circuit including In combination a pair of conductivity controlled current switching devices. a tapped first linear lnduc.or interconnected with sold pair of devices in series circuit relationship across a pair of power supply terminals which are adapted to be connected across a .source of electric potential, a load circuit. means operatively coupled in series circuit relationship with at least one of said pair of devices through a peut of said tapped first linear Inductor for coupling said load circuit across said power supply terminals for clrculaing load current therethrough, and commutation circuit means comprising at least one commutating capacitor and series connected second linear inductor operatively connected between at least one of said power .supply terminals and through said topped first inductor to said pair of devices for commutadng o6 the devices, the series circuit comprised by the commutating capacitor and second lnductor being tuned lo series resonance at a commutating frequency having a period which is substanrlally shorter than the load current conducting periods of .mid power circuit, one of said pair of current switchlng devices being adapted to be infermitrently conductive for discharging the commura'ing capacitor through the tapped first Inductor and thereby terminajng the conduction of the other of said pair of devices.

33. The combination .set forth ln claim 32 further characterized by a unidirectional conducting device directly connected across each of the conductivity controlled current switching devices in reverse polarity parallel ctrcuit relationship for circulating any excess reactive energy of the commutatng capacitor during the commutatlng periods of the conductivity controlled conducting devices.

34. T he combination set forth in claim 32 further.

.26. The combination set forth ln claim 24 further char- 75 characterized by auxiliary circuit means operatively cou- 19 pled to said tapped frst linear inductor for circulating the efnergy stored therein during the commutating period.

35. The combination set forth in claim 32 wherein the :tapped first linear inductor is a winding which is tapped at its midpoint with the two wlndin halves being tightly c oupled so that equal currents flow ng in opposite directions in the winding halva produce ampere-turn eects which cancel each other out.

36. The combination set forth in claim 32 wherein said gate conductivity controlled current switching de- -vices comprise silicon controlled rect ifirs.

37. The combination set forth in claim 32 wherein the conductivity controlled current switching devices comprise silicon controlled rectifiers and wherein the tapped f rst linear inductor is a winding which is tapped at its center point with the two winding halves being tightly coupled so that equal currents flowing in opposite directions in the winding halves produce ampere-turn effects which cancel each other out, and further characterized by auxiliary circuit means opertively coupled to said commutating interval current limiting reactor for circulating any excess energy stored therein during th commutating period, unidirectional conducting device directly conngcted across each of the silicon controlkd rectifiers in reverse polarity, parallel circuit relationship lor circulating any excess reactive energy of the cammutating capacitor during the commutating periods f the gate c0ntplled de vices.

38. he combination set forth in claim 33 wherein said conductivity controlled current switching devices comprise silicon controlled rectiiers, andl said unidirectional conducting devices comprise semiconductor diodes.

39. An improved full-wave bridg'e power circuit including in combination two series circuits connected in parailel circuit relationship across a pair of power supply ter. tninals that in turn are adapted to be connected across a source of electric potential, each of said series circuits being comprised by a pair of conductivity controlled current switching devices and a tapped first linear inductor interconnecting the pair of devices in series circuity relationship, aload circuit interconnecting the tap points of said first inductors, and commutation circuit means comprised by at least one series circuit formed by a commu tating capacitor and series connected second linear incuctor, said last mentioned series circuit being coupled between said powe'rsuppiy and one of said devices in each pair in its conducting condition through the tap point of the second linear inductor connected to such device for commutating o# the same, the series circuit comprised by the commutating capacitor and second inductor being tuned to series resonance at a commutating frequency having a period which is substantially shorter than the load current conducting periods of the power circuit, one of said current switching devices in each pair of series connected devices being intermittently conductive for discharging the commutating capacitor through the tapped first inductor connected thereto and thereby terminating the conduction of the other of said pair of devices.

40. A bridge power circuit according to claim. 39 wherein the commutation circuit means s comprised by a single series circuit formed by a commutating capacitor and series connected second linear inductor connected in parallel circuit relationship with the load.

4l. A bridge power circuit according to claim 39 wherein the commutation circuit means is comprised by two sets of series circuits each formed by a commutating capacitor and series connected second linear inductor wiih each set being connected between the tap point of a respective tapped yrst inductor and a tapped power source connected across the power supply terminals.

42. A bridge power circuit according to claim 39 wherein the commutation circuit means is comprised by four sets of series circuits each formed by a commutating capacitor and series connected second linear inductdr wilh each set being connected in parallel circuit relationship with a respective conductivity controlled current switching device and its series connected winding portion of the tapped first linear inductor connected thereto.

References Cltetl The ioilowing references, cited by the Examiner, are of record in the patented Iilc of this patent or the original patent.

UNITED STATES PATENTS JOHN F. COUCH, Primary Examiner. W. SHOOP, Assistant Examiner. 

